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Advanced RISC architecture
- 133 instruction - most of which can be completed in one clock cycle
- 32 x 8 General Purpose Working Registers + Peripheral Control Registers
- Fully Static Operation
- Working at 16 MHz performance up to 16 MIPS
- Only two clock cycles hardware multiplier
Nonvolatile program and data memory
- The 128K bytes of in-system programmable Flash
Life: 10,000 write / erase cycles
- With independent lock bits, selectable boot code area
Achieved in-system programming via on-chip boot program
The real read - modify - write operations
- 4K bytes of EEPROM
Life: 100,000 write / erase cycles
- 4K bytes of internal SRAM
- Up to 64K bytes of external memory space optimization
- Lock bits can be programmed to implement a software encryption
- Can be achieved in-system programming via ISP
JTAG interface (compatible with the IEEE 1149.1 standard)
- Follow the standard JTAG boundary scan function
- The expansion of the on-chip debug support
- Programming via JTAG interface for Flash, EEPROM, Fuses and Lock bits